1. Field of the Invention
The present invention relates to a non-volatile memory device and a manufacturing method thereof. More specifically, the present invention relates to a 1T1R non-volatile memory device including memory cells each of which includes one transistor and one memory element.
2. Description of the Related Art
In recent years, with progresses of digital technologies, electronic devices such as portable information devices and information home electric appliances have been developed to provide higher functionalities. For this reason, there have been demands for an increase in a capacity of a non-volatile memory device, reduction in write electric power in the non-volatile memory device, reduction in write/read time in the non-volatile memory device, and a longer life of the non-volatile memory device.
Under the circumstances in which there are such demands, the existing flash memory including a floating gate has been developed to provide further miniaturization. Also, it is expected that a non-volatile semiconductor memory element (variable resistance memory) including as a memory section a variable resistance element which stably changes a retained resistance value in response to a voltage pulse applied thereto can achieve further miniaturization, a higher speed, and lower electric power consumption, because its memory cell is implemented with a simple structure.
Therefore, conventionally, a memory cell (1T1R memory cell) which performs a stable memory operation using one transistor and one memory element is created, and high-dense integration is implemented using this cell.
International Publication No. 2009/00808 discloses a 1T1R memory device. In the memory device disclosed in this literature, a bit line BL connected to an upper electrode of a memory element crosses a source line SL connected to a lower electrode of the memory element such that the bit line BL and the source line SL are orthogonal to each other (FIG. 3 of International Publication No. 2009/00808). In this memory device, a variable resistance element RM is connected to a n-type semiconductor region (source, drain) via a plug, a first layer wire, and a plug (z2 region in FIG. 7 of International Publication No. 2009/00808).
Japanese Laid-Open Patent Application Publication No. 2004-355670 discloses a 1T1R memory device. In the memory device disclosed in this literature, a bit line connected to one of electrodes of a memory element and a common source line connected to the other electrode of the memory element extend in parallel with each other (FIG. 4 of Japanese Laid-Open Patent Application Publication No. 2004-355670).